This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device provided with a protective circuit against surge voltages.
The construction indicated in FIG. 1 for the input section of a prior art semiconductor integrated circuit device is shown, e.g., in FIG. 1 of JP-A-No. 59-181044 (laid-open on Oct. 15, 1984).
In the figure, the reference numeral 1 indicates an input terminal; 2 a resistor; 1 a diode; 4 a PMOS; and 5 an NMOS. The PMOS 4 and the NMOS 5 constitute an input buffer circuit, which is a part of the semiconductor integrated circuit device, and the resistor 2 and the diode 3 constitute a protective circuit for the semiconductor integrated circuit device. This protective circuit is necessary to prevent that the transistors 4 and 5 from being destroyed by surge voltages due to electrostatic charge, etc. applied to the input terminal 1. The operation mode of this circuit is as follows.
When a positive surge voltage is applied to the input terminal 1, the diode 3 is broken down and a surge current flows from the input terminal 1 through the resistor 2 and the diode 3 to the ground, which keeps the potential at the node N.sub.1 at a predetermined value and thus protects the transistors 4 and 5.
Next, when a negative surge voltage is applied to the input terminal 1, the diode 3 is turned on and a surge current flows from the ground through the resistor 2 to the input terminal, which keeps the potential at the node N.sub.1 at a predetermined value and thus protects the transistors 4 and 5.
In the prior art circuit, when the resistance of the resistor 2 is augmented, the electrostatic breakdown voltage is increased, but at the same time the delay time due to the time constant determined by the parasitic capacitance as the node N.sub.1 and the resistance of the resistor 2 is increased. To the contrary, if the resistance is reduced in order to ameliorate the speed, the electrostatic breakdown voltage is lowered and therefore it was impossible to reconcile high speed and high reliability.
Further, in the prior art circuit, the resistance of the resistor 2 was fixed at its fabrication and invariable, and thus it performed merely its function as a protective circuit.